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TA0103A Stereo 250W (4) Class-T Digital Audio Amplifier Driver using Digital Power Processing (DPPTM) Technology
Technical Information Revision 3.3 - June 2000
GENERAL DESCRIPTION The TA0103A is a 250W continuous average (4), two channel Amplifier Driver Module which uses Tripath's proprietary Digital Power Processing (DPPTM) technology. Class-T amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.
Applications
Audio/Video Amplifiers/Receivers Pro-audio Amplifiers Automobile Power Amplifiers Subwoofer Amplifiers Home/PC Speaker Systems
Benefits
Reduced system cost with smaller/less expensive power supply and heat sink Signal fidelity equal to high quality ClassAB amplifiers High dynamic range compatible with digital media such as CD and DVD
Features
Class-T architecture Proprietary Digital Power Processing technology Supports wide range of output power levels
"Audiophile" Sound Quality 0.04% THD+N @ 55W, 8 0.03% IHF-IM @ 36W, 8 140W @ 8, 0.1% THD+N, VS = +54V 250W @ 4, 0.1% THD+N, VS = +54V High Power 150W @ 8, 1% THD+N, VS = +54V 300W @ 4, 1% THD+N, VS = +54V High Efficiency 92% @ 155W @ 8, VS = +45V 90% @ 275W @ 4, VS = +45V Dynamic Range = 106 dB Requires only N-Channel MOSFET output transistors High power supply rejection ratio Mute input Outputs short-circuit protected Over- and under-voltage protection Bridgeable, single-ended outputs 38-pin quad package Supports 100kHz BW of Super Audio CD and DVD-Audio (refer to Application Note for specifics)
TYPICAL PERFORMANCE
THD+N versus Output Power
10 5 2 1
20Hz - 22kHz BW f = 1kHz BBM = 65nS Vs = +/-54V Av = 20.75 ST STW38NB20 MOSFET
THD+N (%)
0.5 0.2 0.1
RL= 8
0.05 0.02 0.01 1 2 5 10 20 50 100 200
RL= 4
Output Power (W)
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Absolute Maximum Ratings
SYMBOL Vs V5 VN12 TSTORE TA Positive 5 V Bias Supply Reference Voltage: Nominal +12V referenced to Vsneg Storage Temperature Range Operating Free-air Temperature Range PARAMETER Supply Voltage (Vspos & Vsneg) Value +/-85 6 18 -40 to 150 -20 to +80 UNITS V V V C C
Notes:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Damage will occur to the device if VN12 is not supplied or falls below the recommended operating voltage when VS is within its recommended operating range.
Operating Conditions
SYMBOL Vs V5 VN12 Positive 5 V Bias Supply Reference Voltage: Nominal +12V referenced to Vsneg PARAMETER Supply Voltage (Vspos & Vsneg) MIN. +/- 35 4.5 10.8 5 12 TYP. MAX. +/- 60 5.5 13.2 UNITS V V V
Note: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics for guaranteed specific performance limits.
Electrical Characteristics
TA = 25C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL Iq PARAMETER +45V -45V +5V VN12 Source Current @ POUT = 275W, RL = 4 VSPOS = +45V @ 10% THD+N VSNEG = -45V Source Current for 5V Bias Supply @ POUT = 275W, RL = 4 Source Current for VN12 Supply @ POUT = 275W, RL = 4 Under Voltage (Vspos & Vsneg) Over Voltage (Vspos & Vsneg) High-level Input Voltage (MUTE) Low-level Input Voltage (MUTE) Mute Supply Current (no load, BBM0=BBM1=0) +45V -45V +5V VN12 High-level Output Voltage (HMUTE & OVERLOADB) Low-level Output Voltage (HMUTE & OVERLOADB) Over Current Sense Voltage Threshold Gain Ratio VOUT/VIN, RIN = 0 Offset Voltage, no load, MUTE = Logic low (before nulling) 0.67 0.75 108 300 500 0.375 3.7 17 0.5 3.5 1 0.82 +/-60 3.5 1 2 5 25 2 Quiescent Current (no load, BBM0=BBM1=0) MIN. TYP. 30 36 43 210 7 7 50 80 MAX. 80 60 65 250 7.8 7.8 60 100 +/-35 UNITS mA mA mA mA A A mA mA V V V V mA mA mA mA V V V V/V mV
IS I5 IVN12 Vu Vo VIH VIL IDDMUTE
VOH VOL VTOC AV Voffset
Minimum and maximum limits are guaranteed but may not be 100% tested.
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Performance Characteristics - Single Ended, Vs = +54V
Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. TA = 25C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL POUT PARAMETER Output Pow er (Continuous Average/Channel) CONDITIONS RL = 8 RL = 4 THD+N = 1%, RL = 8 RL = 4 POUT = 55W/Channel, RL = 8 19kHz, 20kHz, 1:1 (IHF), RL = 4 POUT = 36W/Channel A Weighted, RL = 8 , POUT =140W/Ch 0dBr = 60W, RL = 4 , f = 1kHz Input Referenced, 30kHz Bandw idth POUT = 200W/Channel, RL = 8 A Weighted, no signal, input shorted, DC offset nulled to zero, BBM = 145nS THD+N = 0.1%, MIN. TYP. 140 250 150 300 0.04 0.02 101 82 67 92 295 MAX. UNITS W W W W % % dB dB dB % V
THD + N IHF-IM SNR CS PSRR eNOUT
Total Harmonic Distortion Plus Noise IHF Intermodulation Distortion Signal-to-Noise Ratio Channel Separation Pow er Supply Rejection Ratio Pow er Efficiency Output Noise Voltage
Performance Characteristics - Single Ended, Vs = +45V
Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. TA = 25C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL POUT PARAMETER Output Pow er (Continuous Average/Channel) CONDITIONS RL = 8 RL = 4 THD+N = 1%, RL = 8 RL = 4 POUT = 55W/Channel, RL = 8 19kHz, 20kHz, 1:1 (IHF), RL = 4 POUT = 36W/Channel A Weighted, RL = 8 , POUT = 85W/Ch 0dBr = 60W, RL = 4 , f = 1kHz Input Referenced, 30kHz Bandw idth POUT = 155W/Channel, RL = 8 A Weighted, no signal, input shorted, DC offset nulled to zero, BBM = 145nS THD+N = 0.1%, MIN. TYP. 85 150 100 200 0.04 0.03 100 82 67 92 250 MAX. UNITS W W W W % % dB dB dB % V
THD + N IHF-IM SNR CS PSRR eNOUT
Total Harmonic Distortion Plus Noise IHF Intermodulation Distortion Signal-to-Noise Ratio Channel Separation Pow er Supply Rejection Ratio Pow er Efficiency Output Noise Voltage
Minimum and maximum limits are guaranteed but may not be 100% tested.
Notes:
1) 2) V5 = +5V, VN12 = +12V referenced to VSNEG Test/Application Circuit Values: D = MUR120T3 diodes, RIN = 22.1K RD = 33, RS = 0.025,RG = 10 ROCR1 = ROCR2 = 0, LF = 18uH (Amidon core T200-2) CF = 0.22uF, CD = 0.1uF, CIN = 1uF, CBY = 0.1uF Power Output MOSFETs, M = ST STW38NB20 BBMO=0, BBM1=1
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Pin Description
Pin 1 2 3 4 5, 6 7, 8 9, 12 10, 11 13, 14 15, 16 17, 30 18, 29 19 20, 27 21, 26 22, 25 23 24 28 31, 32 33, 34 35 36, 37, 38 Function AGND OVERLOADB V5 MUTE IN2, IN1 BBM0, BBM1 GNDKELVIN1, GNDKELVIN2 OCR2, OCR1 OCS1L+, OCS1LOCS1H-, OCS1H+ LO1COM, LO2COM FDBKN1;FDBKN2 VN12 LO1, LO2 HO1COM, HO2COM HO1, HO2 VSPOS VSNEG PGND OCS2L-, OCS2L+ OCS2H-, OCS2H+ HMUTE NC Description Analog Ground Logic output. When low, indicates that the level of the input signal has overloaded the amplifier. Positive 5 Volts Logic input. When high, both amplifiers are muted. When low (grounded), both amplifiers are fully operational. Single-ended input (Channel 1 & 2) Break-before-make timing control Kelvin connection to speaker ground (Channel 1 & 2) Over-current threshold adjustment (Channel 1 & 2) Over Current Sense resistor, Channel 1 low-side Over Current Sense resistor, Channel 1 high-side Kelvin connection to source of low-side transistor (Channel 1 & 2) Feedback (Channel 1 & 2) Voltage: +12 V from VSNEG. Refer to Application Information section. Low side gate drive output (Channel 1 & 2) Kelvin connection to source of high-side transistor (Channel 1 & 2) High side gate drive output (Channel 1 & 2) Positive supply voltage Negative supply voltage Power Ground Over Current Sense resistor, Channel 2 low-side Over Current Sense resistor, Channel 2 high-side Logic output. When high, indicates that the output stages of both amplifiers are shut off and muted. Not Connected - Must Be Left Floating
38 Pin Quad Package Pin-out (Top View)
38 37 36 35 34 33 32 31 30 29 28
OCS2H+
1
LO2COM
FDBKN2
OCS2L+
OCS2H-
OCS2L-
HMUTE
PGND
NC
NC
NC
AGND OVERLOADB
LO2
27
2
HO2COM
26
3
V5
HO2 VSNEG VSPOS
25
4
MUTE
24
5
IN2 IN1 BBM0 GND KELVIN1 BBM1 GND KELVIN2
23 22 21 20
6 7 8
HO1 H01COM LO1 VN12 19
OCS1H+
LO1COM
9
10
11
12
13
14
15
16
17
Figure 1
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FDBKN1 18
OCS1L+
OCR2
OCR1
OCS1H-
OCS1L-
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Test/Application Circuit
TA0103A
18 FDBKN1 16 OCS1H+ RS 15 OCS1HM 22 CIN RIN V5 10K 1M 0.1 uF 1M MUTE 4 IN1 6 HO1 RG M 20 LO1 RG LF D CBY CF RD CD RL D CBY
.1uF 100uF
VSPOS
Processing & Modulation
21 HO1COM
13 OCS1L+ 17 LO1COM 14 OCS1L-
RS VSNEG
.1uF 100uF
9 GNDKELVIN1 OCR1 ROCR1 OCR2 ROCR2 BBM0 BBM1 7 RS 8 33 OCS2HM 25 CIN RIN V5 10K 1M 0.1 uF 1M NC NC NC V5 0.1 uF 36 37 38 3 AGnd 1 PGnd 28 IN2 5 HO2 RG M 27 LO2 RG LF D CBY CF RD CD RL D CBY
100uF
11 10
2 35
OVERLOADB HMUTE
29 FDBKN2 34 OCS2H+ VSPOS
Processing & Modulation
26 HO2COM
32 OCS2L+ 30 LO2COM 31 OCS2L-
RS VSNEG
.1uF 100uF
12 GNDKELVIN2 23 24 19 VSPOS VSNEG VN12
NC - Not Connected (Must Be Left Floating) Note - Heavy Lines Indicate High-Current Paths
Figure 2
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Typical Performance at Vs = +54V
Efficiency versus Output Power
100 90 80
THD+N versus Output Power
10 5 2 1
20Hz - 22kHz BW f = 1kHz BBM = 65nS Vs = +/-54V Av = 20.75 ST STW38NB20 MOSFET
RL = 4 & 8
RL = 8 RL = 4
Efficiency (%)
70 60 50 40 30 20
THD+N (%)
0.5 0.2 0.1
RL= 8
0.05 0.02 0.01 1 2 5 10 20 50 100 200
RL= 4
10 0 0 50 100 150 200 250
22Hz - 22kHz BW f = 1kHz BBM = 145nS VS = +/-54V Av = 20.75 ST STW38NB20 MOSFET
300
350
400
450
Output Power (W)
Output Power (W)
THD+N versus Frequency RL = 4
10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10 20 50 100 200 500 1k 2k 5k 10k 20k
20Hz - 22kHz BW BBM = 65nS Pout = 10W/Channel Vs = +/-54V Av = 20.75 ST STW38NB20 MOSFET
+10 +0 -10 -20 10Hz - 80kHz BW 19kHz, 20kHz, 1:1 BBM = 65nS Pout = 36W/Channel VS = +/-54V 0dBr = 12Vrms Av = 20.75 ST STW38NB20 MOSFET
Intermodulation Performance HIGH BW (4X) A/D 4 RL =
THD+N (%)
FFT (dBr)
-30 -40 -50 -60 -70 -80 -90 -100
60
100
200
500
1k
2k
5k
10k
20k
30k
Frequency (Hz)
Frequency (Hz)
+0 -10
Channel Separation versus Frequency grounded) RL = 4
20Hz - 22kHz BW BBM = 65nS Pout = 60W/Channel VS = +/-54V Av = 20.75 ST STW38NB20 MOSFET
A-Weighted Noise FFT
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 20Hz - 22kHz BW BBM = 65nS Pout = 0W VS = +/-54V RL = 4 Av = 20.75 ST STW38NB20 MOSFET
Channel Separation (dBr)
-20 -30 -40 -50 -60 -70 -80 -90
-100 -110 -120 20 50 100 200 500 1k 2k 5k 10k 20k
Noise FFT (dBV)
-100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz)
Frequency (Hz)
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Typical Performance at Vs = +45V
THD+N vs Output Power
10 5 2 1
20Hz - 22kHz BW f = 1kHz BBM = 65nS VS = +/-45V Av = 20.75 ST STW38NB20 MOSFET
Efficiency versus Output Power
100 90 80
RL = 8 RL = 4
THD+N (%)
Efficiency (%)
0.5 0.2 0.1 0.05 0.02 0.01 1 2 5 10 20 50
8
4
70 60 50 40 30 20 10 0
22Hz - 22kHz BW f = 1kHz BBM = 145nS VS = +/-45V Av = 20.75 ST STW38NB20 MOSFET
100
200 300
0
25
50
75
100
125
150
175
200
225
250
275
300
Output Power (W)
Output Power (W)
THD+N versus Frequency versus Break Before Make, R L = 8
10 5 2
THD+N versus Frequency versus Break Before Make, R L = 4
10 5 2 1 0.5 0.2 0.1 0.05 0.02
THD+N (%)
1 0.5 0.2 0.1 0.05 0.02 0.01 10 20 50 100 200 500 1k 2k
105nS
THD+N (%)
20Hz - 22kHz BW Pout = 35W/Channel VS = +/-45V Av = 20.75 ST STW38NB20 MOSFET
20Hz - 22kHz BW Pout = 60W/Channel VS = +/-45V Av = 20.75 ST STW38NB20 MOSFET
145nS
145nS
105nS
65nS
65nS
5k 10k 20k
0.01 10
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Frequency (Hz)
THD+N versus Frequency versus Bandwidth, RL = 8
10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 10 20 50 100 200 500 1k 2k
THD+N versus Frequency versus Bandwidth, RL = 4
10 5 2
THD+N (%)
BBM = 65nS Pout = 35W/Channel VS = +/-45V Av = 20.75 ST STW38NB20 MOSFET
BBM = 65nS Pout = 60W/Channel VS = +/-45V Av = 20.75 ST STW38NB20 MOSFET
THD+N (%)
1 0.5 0.2 0.1
30kHz BW
30kHz BW
0.05
22kHz BW
0.02
22kHz BW
5k
10k
20k
0.01
10
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Frequency (Hz)
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Typical Performance
THD+N versus Output Power versus Supply Voltage
10
20Hz - 22kHz BW f = 1kHz BBM = 65nS Av = 20.75 ST STW38NB20 MOSFET
RL = 8
THD+N versus Output Power versus Supply Voltage
10
RL = 4
20Hz - 22kHz BW f = 1kHz BBM = 65nS Av = 20.75 ST STW38NB20 MOSFET
THD+N (%)
THD+N (%)
1
1
36V
45V
0.1
58V
36V
45V
58V
0.1
0.01 1 10
0.01
Output Power (W)
100
1000
1
10
Output Power (W)
100
1000
+10 +0 -10 -20 -30
Intermodulation Performance RL = 8
10Hz - 80kHz BW 19kHz, 20kHz, 1:1 BBM = 65nS Pout = 25W/Channel VS = +/-45V 0dBr = 14Vrms Av = 20.75 ST STW38NB20 MOSFET
+10 +0 -10 -20 -30
Intermodulation Performance RL = 4
10Hz - 80kHz BW 19kHz, 20kHz, 1:1 BBM = 65nS Pout = 36W/Channel VS = +/-45V 0dBr = 12Vrms Av = 20.75 ST STW38NB20 MOSFET
FFT (dBr)
60 100 200 500 1k 2k 5k 10k 20k 30k
FFT (dBr)
-40 -50 -60 -70 -80 -90 -100
-40 -50 -60 -70 -80 -90 -100
60
100
200
500
Frequency (Hz)
Frequency (Hz)
1k
2k
5k
10k
20k 30k
Channel Separation versus Frequency
+0 -10
+0
A-Weighted Noise FFT
-20
Channel Separation (dBr)
-20 -30 -40 -50 -60 -70 -80 -90 -100 20
Noise FFT (dBV)
20Hz - 22kHz BW BBM = 65nS Pout = 60W/Channel @ 4 Pout = 35W/Channel @ 8 VS = +/-45V Av = 20.75 ST STW38NB20 MOSFET
-40 -60 -80
20Hz - 22kHz BW BBM = 65nS Pout = 0W VS = +/-45V RL = 4 Av = 20.75 ST STW38NB20 MOSFET
4 8
-100 -120
50
100
200
500
1k
2k
5k
10k
20k
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Frequency (Hz)
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Functional Description
TA0103A Amplifier Operation Figure 3 is a simplified diagram of one channel (channel 1) of a TA0103A amplifier to assist in understanding its operation.
TA0103A
18 FDBKN1 16 OCS1H+ VSPOS RS 15 OCS1HVBOOT
Over-current Detection
M RG M RL RG
MUTE RIN CIN BBM0 BBM1 IN1
4 6 7 8
22 HO1
Processing & Modulation
21 HO1COM 19 VN12 20 LO1 17 LO1COM
Low-pass Filter
OCR1 ROCR1
11
Over-current Detection
13 OCS1L+ 14 OCS1L9 2 35 GNDKELVIN1 OVERLOADB HMUTE VSPOS VSNEG
RS VSNEG
Over/Under Voltage
V5 3 A Gnd 1 P Gnd 28
23 24
Figure 3: Simplified TA0103A Amplifier The audio input signal (IN1) is fed to the processor internal to the TA0103A, where a modulation pattern is generated. This pattern is spread spectrum and varies between approximately 200kHz and 1.5MHz. Complementary copies of the switching pattern are level-shifted by the MOSFET drivers and output from the TA0103A where they drive the gates (HO1 and LO1) of external power MOSFETs that are connected as a half bridge. The output of the half bridge is a power-amplified version of the switching pattern that switches between VSPOS and VSNEG. This signal is then low-pass filtered to obtain amplified audio. The processor portion of the TA0103A is operated from a 5-volt supply (between V5 and AGND). In the generation of the complementary modulation pattern for the output MOSFETs, the processor inserts a "break-before-make" dead time between when it turns one transistor off and it turns the other one on in order to minimize shoot-through currents in the MOSFETs. The dead time can be programmed by setting the break-before-make control bits, BBM0 and BBM1. Feedback information from the output of the half-bridge is supplied to the processor via FDBKN1. Additional feedback information to account for ground bounce is supplied via GNDKELVIN1.
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The MOSFET drivers in the TA0103A are operated from voltages obtained from VN12 and LO1COM for the low-side driver, and VBOOT (generated internal to the TA0103A) and HO1COM for the highside. Only N-Channel MOSFETs are required for both the top and bottom of the half bridge. VN12 must be a stable 12V above VSNEG. The gate resistors, RG, are used to control MOSFET slew rate and thereby minimize voltage overshoots. Over- and Under-Voltage Protection The TA0103A senses the power rails through VSPOS and VSNEG for over- and under-voltage conditions. The over- and under-voltage limits are Vo and Vu respectively as specified in the Electrical Characteristics table. If the supply voltage exceeds Vo or drops below Vu, the TA0103A shuts off the output stages of the amplifiers and asserts a logic level high on HMUTE. The removal of the over-voltage or under-voltage condition returns the TA0103A to normal operation and returns HMUTE to a logic level low. Please note that the limits specified in the Electrical Characteristics table are at 25C and these limits may change over temperature. Over-current Protection The TA0103A has over-current protection circuitry to protect itself and the output transistors from short-circuit conditions. The TA0103A uses the voltage across a resistor, RS (measured via OCS1H+, OCS1H-, OCS1L+ and OCS1L-), that is in series with each output MOSFET to detect an over-current condition. RS and ROCR are used to set the over-current threshold. The OCS pins must be Kelvin connected for proper operation. See "Circuit Board Layout" in Application Information for details. An over-current condition will cause the TA0103A to shut off the output stages of the amplifiers and supply a logic level high on HMUTE. The occurrence of an over-current condition is latched in the TA0103A and can be cleared by toggling the MUTE input or cycling power. Overload When logic low, the OVERLOADB pin indicates that the level of the input signal has overloaded the amplifier and that the audio output signal is starting to distort. The OVERLOADB signal is active only while an overload is present. The OVERLOADB signal can be used to control a distortion indicator light or LED through a simple buffer circuit. Mute When a logic high signal is supplied to MUTE, both amplifier channels are muted (both high- and low-side transistors are turned off) and a logic level high is output on the HMUTE pin. When a logic level low is supplied to MUTE, both amplifiers are fully operational and a logic level low is supplied on HMUTE. There is a delay of approximately 200 milliseconds between the de-assertion of MUTE and the un-muting of the TA0103A.
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Application Information
Amplifier Gain and Input Resistor Selection The value of the input resistor, RIN, is based on the required voltage gain, AV, of the amplifier according to: AV = 538 x103/(RIN + 5000) where RIN = Input resistor value in ohms. Input Capacitor Selection CIN can be calculated once a value for RIN has been determined. CIN and RIN determine the input low-frequency pole. Typically this pole is set at 10 Hz. CIN is calculated according to: CIN = 1/((2 x FP)(RIN + 5000)) where: RIN = Input resistor value in ohms. FP = Input low frequency pole (typically 10Hz). DC Offset Adjust While the DC offset voltages that appear at the speaker terminals of a TA0103A amplifier are typically small, Tripath recommends that any offsets during operation be nulled out of the amplifier with a circuit like the one shown connected to IN1 and IN2 in the Test/Application Circuit. It should be noted that the DC voltage on the output of a TA0103A amplifier with no load in mute mode is approximately 2.5V. This offset does not need to be nulled. The output impedance of the amplifier in mute mode is approximately 10 KOhms. This means that the 2.5V drops to essentially zero when a typical load is connected. Supply Voltage and Output Power The relationship between the bipolar power supply voltage needed, VS, for a given RMS output power, POUT, into a given load, RL, at a given level of THD (total harmonic distortion) is approximated by: VS = (2 x RL x POUT) 0.5/(K x RL/(RL + RON + RS + RCOIL)) where: RON = The at-temperature RDSON of the output transistors, M. RCOIL = Resistance of the output filter inductor. RS = Sense Resistor K = THD Factor, a number fixed by the algorithms in the TA0103A's signal processor that provides the relationship between THD at full output power of the amplifier and VS. K corresponds to THD at full output power as follows: THD 0.1% 1% 10% K 0.83 0.95 1.09
Typical measurement graphs of POUT versus supply voltage for various levels of THD are also included in this data sheet to help determine the supply voltage.
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Bridged Operation Note that the two channels of a TA0103A amplifier can be used to provide a single, bridged amplifier of almost four times the output power of one of the single-ended amplifier channels. To configure a bridged amplifier, the input to one TA0103A channel must be the inverted signal of the input to the other channel. Low-frequency Power Supply Pumping A potentially troublesome phenomenon in single-ended switching amplifiers is power supply pumping. This is caused by current from the output filter inductor flowing into the power supply output filter capacitors in the opposite direction as a DC load would drain current from them. Under certain conditions (usually low-frequency input signals), this current can cause the supply voltage to "pump" (increase in magnitude) and eventually cause over-voltage/under-voltage shut down. Moreover, since over/under-voltage are not "latched" shutdowns, the effect would be an amplifier that oscillates between on and off states. If a DC offset on the order of 0.3V is allowed to develop on the output of the amplifier (see "DC Offset Adjust"), the supplies can be boosted to the point where the amplifier's over-voltage protection triggers. One solution to the pumping issue is to use large power supply capacitors to absorb the pumped supply current without significant voltage boost. The low frequency pole used at the input to the driver determines the value of the supply capacitor required. This works for AC signals only. Another solution to the supply pumping problem uses the fact that music has low frequency information that is correlated in both channels (it is in phase). This information can be used to eliminate boost by putting the two channels of a TA0103A amplifier out of phase with each other. This works because each channel is pumping out of phase with the other, and the net effect is a cancellation of pumping currents. The phase of the audio signals needs to be corrected by connecting one of the speakers in the opposite polarity as the other channel.
VN12 Supply VN12 is an additional supply voltage required by the TA0103A. VN12 must be 12 volts more positive than the nominal VSNEG. VN12 must track VSNEG, so if an unregulated supply is used for VSNEG, the design of the supply for VN12 must behave accordingly. Generating the VN12 supply requires some care. The proper way to generate the voltage for VN12 is to use a 12V-supply voltage referenced to the VSNEG supply rather than to ground (PGND). Figure 4 shows the correct way to power the TA0103A:
VSPOS V5 VS 5V
PGND
AGND VN12
VS 12V VSNEG
Figure 4 One method to generate the VN12 supply voltage is to use a positive 12V IC regulator to drop PGND down to 12V (relative to VSNEG). Care must be exercised with this method because some IC regulators such as the LM340 series will not function properly with a large voltage drop across the regulator, resulting in damage to the TA0103A.
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Generating the VN12 voltage per Figure 5 is NOT recommended. Most power supplies only sink current from the negative terminal and will not be capable of sourcing the current required by VN12. Furthermore, problems can arise since VN12 will not track movements in VSNEG.
VSPOS V5 VS 5V A GND P GND VS -33V VN12 VSNEG
Figure 5 Setting Over-current Threshold RS and ROCR determine the value of the over-current threshold, ISC: ISC x RS = (VTOC x 9100)/(9100 + ROCR) where: RS and ROCR are in ISC = 3 x IRMS = 3 x (POUT/RL) 0.5 (Over-current is typically set for 3 x RMS current) VTOC = Over-current sense threshold voltage (See Electrical Characteristics Table) = 0.75V typically when ROCR = 0, RS = (0.75)/ISC Note that RS will dissipate approximately (IRMS)2 x RS of power. To set an ISC of 30A, for example, with ROCR = 0, means that RS = 25m and RS must dissipate 2.5W on average. If ROCR = 9.1K, then to set ISC = 30A, RS will be 12.5m and will only have to dissipate 1.13W on average. As high-wattage resistors are usually only available in a few low-resistance values (10m, 25m and 50m), ROCR can be used to adjust for a particular over-current threshold using one of these values for RS. Output Transistor Selection The key parameters to consider when selecting a MOSFET to use with the TA0103A are drainsource breakdown voltage (BVdss), gate charge (Qg), and on-resistance (RDS(ON)). The BVdss rating of the MOSFET needs to be selected to accommodate the voltage swing between VSPOS and VSNEG as well as any voltage peaks caused by voltage ringing due to switching transients. With a `good' circuit board layout, a BVdss that is 50% higher than the VSPOS and VSNEG voltage swing is a reasonable starting point. The BVdss rating should be verified by measuring the actual voltages experienced by the MOSFET in the final circuit. Ideally a low Qg (total gate charge) and low RDS(ON) are desired for the best amplifier performance. Unfortunately, these are conflicting requirements since RDS(ON) is inversely proportional to Qg for a typical MOSFET. The design trade-off is one of cost versus performance. A lower RDS(ON) means lower I2RDS(ON) losses but the associated higher Qg translates into higher switching losses (losses = Qg x 12 x 1.2MHz). A lower RDS(ON) also means a larger silicon die and higher cost. A higher RDS(ON) means lower cost and lower switching losses but higher I2RDSON losses.
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The following table lists BVdss, Qg and RDS(ON) for MOSFETs that Tripath has used with the TA0103A: Mfg. Part Number ST STW34NB20 ST STW38NB20 ST STP19NB20 IR IRF640 Gate Resistor Selection The gate resistors, RG, are used to control MOSFET switching rise/fall times and thereby minimize voltage overshoots. They also dissipate a portion of the power resulting from moving the gate charge each time the MOSFET is switched. If RG is too small, excessive heat can be generated in the driver. Large gate resistors lead to slower MOSFET switching, which requires a larger breakbefore-make (BBM) delay. Tripath recommends using an RG of 10 when the Qg of the MOSFET is less than 70nC and 5.6 when the Qg is greater than 70nC. Break-Before-Make (BBM) Timing Control The half-bridge power MOSFETs require a deadtime between when one transistor is turned off and the other is turned on (break-before-make) in order to minimize shoot through currents. BBM0 and BBM1 are logic inputs (connected to logic high or pulled down to logic low) that control the breakbefore-make timing of the output transistors according to the following table. Note that if either BBM0 or BBM1 are left floating, they are pulled to a logic low level internal to the TA0103A.
BBM1 BBM0
BVdss 200 200 200 200
Qg (Max) (nanoCoulombs) 80 95 40 70
RDS(ON) (Max) (Ohms) 0.075 0.065 0.18 0.18
0 0 1 1
0 1 0 1
Delay 145nS 105nS 65nS 25nS
The tradeoff involved in making this setting is that as the delay is reduced, distortion levels improve but shoot-through and power dissipation increase. Since the actual amount of BBM required is dependent upon other component values and circuit board layout, the value selected should be verified in the actual application circuit/board. It should also be verified under maximum temperature and power conditions since shoot-through in the output MOSFETs can increase under these conditions, possibly requiring a higher BBM setting than at room temperature. Clamping Diodes The purpose of the diode, D, across each of the output MOSFETs is to clamp the voltages the MOSFET experiences to levels within its rating to prevent damage. Tripath recommends that fastrecovery or schottky diodes be used for this purpose (depending on the supply voltage used). The breakdown voltage rating of this diode should be similar to that of the MOSFET. Also, the forward voltage drop of this diode should be less than that of the internal body diode of the MOSFET. MOSFET Bypass Capacitor Bypass capacitors, CBY, are necessary for each output MOSFET at the nodes shown in the Test/Application Circuit to damp voltage ringing at these nodes due to the high currents flowing through the parasitic (circuit board trace) inductance. CBY should be 0.1uF and have the appropriate voltage rating. They should be physically located as close to the MOSFET leads as possible.
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Turn-on & Turn-off Noise If turn-on or turn-off noise is present in a TA0103A amplifier, the cause is frequently due to other circuitry external to the TA0103A. While the TA0103A has circuitry to suppress turn-on and turn-off transients, the combination of the power supply and other audio circuitry with the TA0103A in a particular application may exhibit audible transients. One solution that will completely eliminate turnon and turn-off pops and clicks is to use a relay to connect/disconnect the amplifier from the speakers with the appropriate timing at power on/off. The relay can also be used to protect the speakers from a component failure (e.g. shorted output MOSFET), which is a protection mechanism that some amplifiers have. Circuitry external to the TA0103A would need to be implemented to detect these failures. Output Filter Design One advantage of Tripath amplifiers over PWM solutions is the ability to use higher-cutoff-frequency filters. This means any load-dependent peaking/droop in the 20kHz audio band potentially caused by the filter can be made negligible. This is especially important for applications where the user may select a 4-Ohm or 8-Ohm speaker. Furthermore, speakers are not purely resistive loads and the impedance they present changes over frequency and from speaker model to speaker model. Tripath recommends designing the filter as a 2nd order, 80kHz LC filter. Tripath has obtained good results with LF = 18uH and CF = 0.22uF for a nominal impedance of 8 . The core material of the output filter inductor has an effect on the distortion levels produced by a TA0103A amplifier. Tripath recommends low-mu type-2 iron powder cores because of their low loss and high linearity. Tripath also recommends that an RC damper be used after the LC low-pass filter. No-load operation of a TA0103A amplifier can create significant peaking in the LC filter, which produces strong resonant currents that can overheat the output MOSFETs and/or other components. The RC dampens the peaking and prevents problems. Tripath has obtained good results with RD = 33 and CD = 0.1uF. It is highly recommended that the design process for a TA0103A amplifier include an analysis of the interaction of intended speaker(s) with the LC filter and RC damper to ensure the desired frequency response is attained. Component values for the LC filter and RC damper may need to be altered from the Tripath suggestions to achieve the required response. Grounding Tripath recommends not connecting analog ground (AGND) to power ground (PGND) externally, as this connection is already made internal to the TA0103A. Circuit Board Layout Considerable care needs to be taken in the layout of the circuit board for a TA0103A amplifier. The high currents flowing through PCB traces and the inductive effects due to the switching frequencies involved can cause large overshoot and undershoot voltages if care is not taken. A general rule to follow is to keep the PCB trace of each signal path to/from each lead of each output MOSFET as short as physically possible. Certain circuit functions in a TA0103A amplifier cannot share PCB return paths with other functions because of the resistive and inductive effects of the switching currents and frequencies used. These so-called `Kelvin' paths must each have a dedicated PCB trace from the TA0103A to their destination. The following signals should be treated as Kelvin paths: OCS1H+, OCS1H-, OCS1L+, OCS1L-, OCS2H+, OCS2H-, OCS2L+, OCS2L-, FDBKN1, FDBKN2, GNDKELVIN1 and GNDKELVIN2.
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Performance Measurements of a TA0103A Amplifier Tripath amplifiers operate by modulating the input signal with a high-frequency switching pattern. This signal is sent through a low-pass filter (external to the Tripath amplifier) that demodulates it to recover an amplified version of the audio input. The frequency of the switching pattern is spread spectrum and typically varies between 200kHz and 1.5MHz, which is well above the 20Hz - 22kHz audio band. The pattern itself does not alter or distort the audio input signal but it does introduce some inaudible noise components. The measurements of certain performance parameters, particularly those that have anything to do with noise, like THD+N, are significantly affected by the design of the low-pass filter used on the output of the TA0103A and also the bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off just past the audio band or the bandwidth of the measurement instrument ends there, some of the inaudible noise components introduced by the Tripath amplifier switching pattern will get integrated into the measurement, degrading it. One advantage of Tripath amplifiers is that they do not require large multi-pole filters to achieve excellent performance in listening tests, usually a more critical factor than performance measurements. Though using a multi-pole filter may remove high-frequency noise and improve THD+N type measurements (when they are made with wide-bandwidth measuring equipment), these same filters can increase distortion due to inductor non-linearity. Multi-pole filters require relatively large inductors, and inductor non-linearity increases with inductor value. Efficiency Of A TA0103A Amplifier The efficiency, , of an amplifier is: = POUT/PIN The power dissipation of a TA0103A amplifier is primarily determined by the on resistance, RON, of the output transistors used, and the switching losses of these transistors, PSW. For a TA0103A amplifier, PIN (per channel) is approximated by: PIN = PDRIVER + PSW + POUT ((RS + RON + RCOIL + RL)/RL)2 where: PDRIVER = Power dissipated in the TA0103A = 1.6W/channel PSW = 2 x (0.015) x Qg (Qg is the gate charge of M, in nano-coulombs) RCOIL = Resistance of the output filter inductor (typically around 50m) For an 155W RMS per channel, 8 load amplifier using STW38NB20 MOSFETs, and an RS of 50m, PIN = PDRIVER + PSW + POUT ((RS + RON + RCOIL + RL)/RL)2 = 1.6 + 2 x (0.015) x (95) + 155 x ((0.025 + 0.11 + 0.05 + 8)/8)2
= 1.6 + 2.85 + 162
= 166.7W In the above calculation the RDS (ON) of 0.065 was multiplied by a factor of 1.7 to obtain RON in order to account for some temperature rise of the MOSFETs. (RDS (ON) typically increases by a factor of 1.7 as for a typical MOSFET as temperature increases from 25C to 170C.) So, = POUT/PIN = 155/166.7 = 93% This compares to the 90% measured efficiency (see Typical Performance graphs).
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Technical Documentation
Please refer to the Tripath "Application Notes" section on our web page (http://www.tripath.com/html/tech.htm#appnotes) for more information regarding evaluation, test and design of Class-T amplifiers.
Package Information
38 Pin Quad Module
180mil. (4.6mm) 750mil. (19mm) 180mil. (4.6mm) 485mil. (12.3mm) 1 2 100mil. (2.54mm) 2030mil. (51.6mm) MAX 2087mil. (53mm) 3 4 5 1670mil. (42.4mm) 6 7 8 27 26 25 24 23 22 21 20 38 37 36 35 34
2500mil. (63.5mm)
33
32
31
30
29
28
9
10
11
12
13
14
15
16
17
18
19
2858mil. (72.6mm) MAX 2913mil. (74mm)
565mil. (14.34mm) MAX 610mil (15.5mm) 336mil. (8.54mm) 236mil. (6mm)
30mil. (0.85mm) 100mil. (2.54mm)
Phyco Socket: 4150-1 x 8SF1 8 position header female 4150-1 x 1SF1 11 position header female Figure 6
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This data sheet contains the design specifications for a product in development. Specifications may change in any manner without notice. Tripath and Digital Power Processing are trademarks of Tripath Technology Inc. Other trademarks referenced in this document are owned by their respective companies. Tripath Technology Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Tripath does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. TRIPATH'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF THE PRESIDENT OF TRIPATH TECHNOLOGY INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in this labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
CONTACT INFORMATION
World Wide Sales Offices
United States & Europe SE Asia & China Japan & Korea Jim Hauer Eugene Hsu Osamu Ito jhauer@tripath.com ehsu@tripath.com ito@tripath.com 408.567.3089 886.2.2653.7428 81.42.334.2433
TRIPATH TECHNOLOGY, INC
3900 Freedom Circle Santa Clara CA 95054 408.567.3000 www.tripath.com
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